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1M x 16-Bit Dynamic RAM (1k & 4k -Refresh)
HYB3116160BSJ/BST(L)-50/-60/-70 HYB3118160BSJ/BST(L)-50/-60/-70
Advanced Information
* * *
1 048 576 words by 16-bit organization 0 to 70 C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns
* *
* * * * * * * *
Single + 3.3 V ( 0.3 V) supply Low power dissipation max. 720 active mW ( HYB3118160BSJ/BST-50) max. 648 active mW ( HYB3118160BSJ/BST-60) max. 576 active mW ( HYB3118160BSJ/BST-70) max. 360 active mW ( HYB3116160BSJ/BST-50) max. 324 active mW ( HYB3116160BSJ/BST-60) max. 288 active mW ( HYB3116160BSJ/BST-70) 7.2 mW standby (LV-TTL) 3.6 mW standby (LV-CMOS) 720 W standby for L-version Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh Fast page mode capability 2 CAS / 1 WE All inputs, outputs and clocks fully LV-TTL-compatible 1024 refresh cycles / 16 ms for HYB 3118160BSJ 4096 refresh cycles / 64 ms for HYB 3116160BSJ Plastic Package: P-SOJ-42-1 400 mil P-TSOPII-50/44-1 400mil
Semiconductor Group
1
1.96
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
The HYB 3116(8)160BSJ/BST is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits. The HYB 3116(8)160BSJ/BST utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3116(8)160BSJ/BST to be packaged in standard SOJ-42 and TSOPII-50/44 plastic package with 400mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V ( 0.3 V) power supply, direct interfacing with highperformance logic device families.The HYB3116160BSTL parts have a very low power sleep mode" suppported by Self Refresh. Ordering Information Type
HYB 3116160BSJ-50 HYB 3116160BSJ-60 HYB 3116160BSJ-70 HYB 3118160BSJ-50 HYB 3118160BSJ-60 HYB 3118160BSJ-70 HYB 3116160BST-50 HYB 3116160BST-60 HYB 3116160BST-70 HYB 3118160BST-50 HYB 3118160BST-60 HYB 3118160BST-70
Ordering Code
on request on request on request on request on request on request on request on request on request on request on request on request
Package
P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil
Descriptions
DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)
Pin Names
A0 to A9 A0 to A9 A0 to A11 A0 to A7 RAS OE I/O1-I/O16 UCAS LCAS WE VCC VSS N.C. Row Address Inputs for 1k-refresh version HYB3118160BSJ/BST Column Addess Inputs for 1k-refresh version HYB3118160BSJ/BST Row Address Inputs for 4k-refresh version HYB3116160BSJ/BST Column Address Inputs for 4k-refresh version HYB3116160BSJ/BST Row Address Strobe Output Enable Data Input/Output Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Power Supply (+ 3.3 V) Ground (0 V) not connected
Semiconductor Group
2
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
P-SOJ-42 (400 mil) Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS A11/NC A10/NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Vss I/O1 I/O16 I/O2 I/O3 I/O15 I/O4 I/O14 Vcc I/O13 I/O5 Vss I/O6 I/O12 I/O7 I/O11 I/O8 I/O10 N.C. I/O9 N.C. LCAS N.C. UCAS N.C. OE WE A9 RAS A11/N.C. A8 A10.N.C. A7 A0 A6 A1 A5 A2 A4 A3 Vss Vcc
Vcc
P-TSOPII-50/44 (400mil)
1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C.
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss
*) A11 and A10 are not connected for HYB3118160BSJ/BST (1k-refresh version)
Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1-I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z 3 I/O9-I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write NOP
Semiconductor Group
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
8
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(8)
8
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (12) 12 Row
256 x16
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096x256x16
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3116160BSJ
Semiconductor Group
4
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (10) 10 Row 10
1024 x16
Address Buffers(10)
10
Decoder 1024
Row
Memory Array 1024x1024x16
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3118160BSJ
Semiconductor Group
5
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Soldering time.............................................................................................................................10 s Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage..................................................................................................-0.5 V to 4.6 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics (values in brackets for HYB3116160BSJ)
TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, tT = 5 ns
Parameter Input high voltage Input low voltage TTL Output high voltage (IOUT = - 2 mA) TTL Output low voltage (IOUT = 2 mA) CMOS Output high voltage (IOUT = - 100 A) CMOS Output low voltage (IOUT = 100 A) Input leakage current,any input (0 V VIH Vcc + 0.3V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT Vcc + 0.3V) Average VCC supply current: -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) ICC2 Semiconductor Group 6 - 2 mA - Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 - 0.2 10 10 2.0 - 0.5 2.4 - Vcc-0.2 - - 10 - 10 Unit Test Condition V V V V V V A A
1) 1) 1) 1) 1) 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1
1)
- - -
200(100) mA 180 (90) mA 160 (80) mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
DC Characteristics (values in brackets for HYB3116160BSJ) (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, tT = 5 ns Parameter Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling: CAS = VIH, tRC = tRC min.) Average VCC supply current, during fast page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling, tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Standby VCC supply current (L-version) (RAS = CAS = VCC - 0.2 V) Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS, CAS cycling, tRC = tRC min.) Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc--0.2V or 0.2V)
Symbol
Limit Values min. max.
Unit Test Condition
2) 4) 2) 4) 2) 4)
ICC3
- - - 200(100) mA 180 (90) mA 160 (80) mA
ICC4
- - - 55 (40) 50 (35) 45 (30) mA mA mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
ICC5 ICC5 ICC6
- -
1 200
mA A
1)
1)
- - -
200(100) mA 180 (90) mA 160 (80) mA
2) 4) 2) 4) 2) 4)
ICC7
_
1 250
mA A
L-version
Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A11) Input capacitance (RAS, UCAS, LCAS, WE, OE) I/O capacitance (I/O1-I/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
7
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 -70 max. - - 10k 10k - - - - 50 35 - - - 50 16 64 256 max. min. - - 10k 10k - - - - 37 25 110 40 60 15 0 10 0 15 20 15 15 60 - 50 16 64 256 5 3 - - - max. min. - - 10k 10k - - - - 45 30 - - - 50 16 64 256 130 50 70 20 0 10 0 15 20 15 20 70 5 3 - - -
Unit Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for HYB3118160 Refresh period for HYB3116160 Refresh period for L-versions tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms 7
Read Cycle
Access time from RAS Access time from CAS OE access time Read command setup time Read command hold time Read command hold time referenced to RAS tRAC tCAC tOEA tRCS tRCH tRRH - - - - 25 0 0 0 50 13 25 13 - - - - - - - - 30 0 0 0 60 15 30 15 - - - - - - - - 35 0 0 0 70 20 35 20 - - - - ns ns ns ns ns ns ns ns 11 11 8, 9 8, 9 8,10
Access time from column address tAA Column address to RAS lead time tRAL
Semiconductor Group
8
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 0 0 0 0 15 15 - 15 15 - - - 0 0 0 0 20 20 -70 max. - 20 20 - - - max. min. - 13 13 - - - max. min.
Unit Note
CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay
tCLZ tOFF tOEZ tDZO tCDD tODD
0 0 0 0 13 13
ns ns ns ns ns ns
8 12 12 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 8 8 0 13 13 0 10 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - 10 10 0 20 20 0 15 0 - - - - - - - - ns ns ns ns ns ns ns ns 16 16 13 15
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time Data to CAS low delay tDS tDH tDZC
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tRWC tRWD tCWD tOEH 126 68 31 43 13 - - - - - 150 80 35 50 15 - - - - - 180 95 45 60 20 - - - - - ns ns ns ns ns 15 15 15
Column address to WE delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width tPC tCP tCPA tRAS 35 10 - 50 - - 30 40 10 - - - 35 45 10 - - - 40 ns ns ns 7
200k 60
200k 70
200k ns
Semiconductor Group
9
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 35 - 40 -70 max. - max. min. - max. min.
Unit Note
CAS precharge to RAS Delay
tRHPC
30
ns
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time CAS precharge to WE tPRWC tCPWD 71 48 - - 80 55 - - 95 65 - - ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time tCPT 35 - 40 - 40 - ns
Self Refresh Cycle
RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS 100k _ 95 -50 _ _ 100k _ 110 -50 _ _ 100k _ 130 -50 _ _ ns ns ns 17 17 17
Semiconductor Group
10
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA). 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.
Semiconductor Group
11
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tRCH
V
Address
AAAAAAAA IH AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
VIL
Row
Row
tRAH
V
tRCS
tRRH tAA tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
WE
AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA V AAAAAAAAAAAAAAAAAAAAAAAAAA
IL
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC
tCDD tODD tCAC
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
I/O (Inputs)
V
tDZO
AAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
tOFF tOEZ
I/O (Outputs) V
V OH Hi Z OL
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Valid Data Out
Hi Z
tRAC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
"H" or "L"
WL1
Read Cycle Semiconductor Group 12
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
. Row
Address
IH AAAAAAA AAAAAAA
Row
VIL
tRAH
V
tWCS t WP
tCWL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tWCH tRWL
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
"H" or "L"
WL2
Write Cycle (Early Write) Semiconductor Group 13
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address V AAAAAAAAA Row AAAAAAAAA AAAAAAAAA IL AAAAAAAAA
V AAAAAAAAA IHAAAAAAAAA AAAAAAAAA
. Row
tRAH
V
WE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCWL tRWL tWP
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEH
V
OE
IH AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
VIL
tDZO tDZC
I/O (Inputs)
V IH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tODD tDS tOEZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tDH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
Valid Data
tCLZ tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
I/O (Outputs) V
V OH OL
Hi-Z
Hi-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL3
Write Cycle (OE Controlled Write) Semiconductor Group 14
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRWC tRAS
V
tRP
RAS
IH
VIL V
tCSH tRCD tRSH tCAS tCRP
IH
UCAS LCAS
VIL
tRAH tASR
V
tCAH tASC
tASR
Row
Address
IH AAAA AAAA AAAA
AAAA AAAA AAAA
VIL
Row
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
tRAD
V
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tAWD
tCWD tRWD
tRWL tWP
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
WE
VIL
tAA tRCS
V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEA
tOEH
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
OE
VIL
tDZO tDZC
V
AAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tDS
tDH
Valid Data in
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
I/O (Inputs)
VIL
tCLZ tCAC
tODD tOEZ
AAAAAA AAAAAA Data AAAAAA AAAAAA AAAAAA Out AAAAAA
I/O (Outputs) V OL
V OH
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL4
Read-Write (Read-Modify-Write) Cycle Semiconductor Group 15
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tRCD
V IH
tCAS
tCP
tCAS
tRHCP tRSH tCAS
tCRP
UCAS LCAS
VIL
tCSH tRAH tASR tCAH
Column
V
tASC
tASC
tCAH
tCAH tASC AAAAAAAAA AAAAAAAAA AAAAAAAAA Column AAAAAAAAA AAAAAAAAA AAAAAAAAA tRCS
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAA tRRH AAAAAAA
tASR
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
Address
AAAAA IH AAAAA AAAAA AAAAA Row AAAAA AAAAA AAAAA AAAAA AAAAA VIL AAAAA AAAAA AAAAA tRAD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
Row
tRCH
tRCH tRCS
V IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRCS
WE
VIL
tAA
V
AAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
tCPA tAA tOEA
tOEA
tCPA tAA tOEA tDZC
OE
VIL
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tDZC tDZO tODD
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
tDZC tDZO tODD tDZO
tCDD tODD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tOFF
I/O (Inputs)
V
IH AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
VIL
tCAC tCLZ
tCAC tCLZ
tRAC
OH I/O (Outputs) V OL V
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
tCAC tCLZ
tOEZ
tOEZ
tOEZ
AAAAA AAAAA AAAAA Valid AAAAA AAAAA Data Out AAAAA AAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
FPM1
Fast Page Mode Read Cycle Semiconductor Group 16
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRAS
V IH
tRP
RAS
VIL
tPC tRCD
V IH
tRSH tCP tCAS tCAS tCRP
tCAS
CAS
VIL
tRAH tASR
V IH AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRAL tCAH tASC tASC
AAAAAAAAAA AAAAAAAAAA
tCAH tASC
AAAAAAAAAA AAAAAAAAAA
tCAH
tASR
AAAAAAAAA AAAAAAAAA
Address
VIL
Row
AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA
tRAD tWCS
V
tCWL tWCH tWP
tWCS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
tCWL tWCH tWP
tWCS
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tCWL tRWL
WE
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tWCH tWP AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
VIL
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDH tDS
I/O (Inputs)
V
AAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
tDH tDS
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tDH tDS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
VIL
Valid Data In
Valid Data In
Valid Data In
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Outputs) V OL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
V
HI-Z
"H" or "L"
FPM2
Fast Page Mode Early Write Cycle Semiconductor Group 17
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tCPWD tCWD
tAWD
tOEA
tCPWD tCWD
tOEA
tCAH
tRWD tCWD
tAWD
tOEA
tCAH
tDZC tCLZ tDZO
tCSH
Column
tASC
tAA
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWP
Data In
tOEH
tOEZ tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column Address
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWP
tOEH
Data In
tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tASC
tCWL
tDZC
tCAC tAA
tCAH
tCPA
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEH
tWP
Data In
tDH tOEZ tDS
AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRAL
tRWL tCWL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRP
tCRP
tASR
Row
tODD
tCAS
tPRWC tCAS
tRAS
tODD
tOEZ
tAWD
tASC
tCPA tDZC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCWL
tCP
tAA
AAAAAA AAAAAA AAAAAA AAAAAA
tODD
tCAS
I/O (Inputs) V IL
Fast Page Mode Read-Modify- Write Cycle Semiconductor Group 18
OH I/O (Outputs) V
IH
IH
IH
IH
IH
IH
V IL
V IL
V IL
V IL
V
V IL
V
V
V
Address
UCAS LCAS
RAS
V
WE
OE
V
V
OL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Row
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
"H" or "L"
tRAD
tRAH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRCD
tRCS
tRAC
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tRSH
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCRP tRPC
V IH
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
CAS
VIL
tRAH tASR
tASR
Row
V
Address
IH AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
VIL
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Outputs) V OL
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
V
HI-Z
"H" or "L"
WL9
RAS-Only Refresh Cycle
Semiconductor Group
19
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCP
tCSR tCHR tRPC
tCRP
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
V
UCAS LCAS
IH
VIL
tWRP tWRH
V IH AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
VIL
tOEZ
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD
OH I/O (Outputs)VOL V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL10
CAS-Before-RAS Refresh Cycle Semiconductor Group 20
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
V
tRSH tCHR tCRP
UCAS LCAS
IH
VIL
tRAD tASC tASR tRAH
AAAAA AAAAA AAAAA AAAAA
tWRP tCAH tWRH tASR
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA AAAAAAA VIL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRCS
WE
V AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tRRH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tAA tOEA
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
tDZO
V
tODD tCAC tCLZ
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
I/O (Inputs)
IH
VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOFF tOEZ
Valid Data Out
tRAC
OH I/O (Outputs) V OL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
V
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
HI-Z
"H" or "L"
WL11
Hidden Refresh Cycle (Read) Semiconductor Group 21
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRC tRP
V IH
tRC tRAS tRP
tRAS
RAS
VIL
tRCD
V IH
tRSH
tCHR
tCRP
UCAS LCAS
VIL
tRAD tRAH tASR
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tASC tCAH
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA
AAAAAAA Row AAAAAAA VIL AAAAAAA AAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Row
tWCS
tWCH tWP
tWRP
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tWRH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
WE
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
VIL
tDS
I/O (Input)
V AAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA IL AAAAAAAAAAAAAAA
tDH
Valid Data
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Output) V OL
V
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL12
Hidden Refresh Cycle (Early Write) Semiconductor Group 22
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRP
V
tRASS
tRPS
RAS
IH
VIL
tRPC tCSR tCHS tCP
tCRP
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
V
CAS
IH
VIL
tWRP tWRH
V
WE
IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD tOEZ
OH I/O (Outputs) V OL
V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL13
CAS before RAS Self Refresh Cycle
Semiconductor Group
23
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
tRAS
Read Cycle:
RAS
V IH V IL
tRP
tCSR
CAS
V IH V IL
tCHR
tCP
tRSH tCAS tRAL
Address
V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tASC
tCAH tAA tCAC
tASR
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Column
tWRP
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
V IL AAAAAAAAAAAAA
V IHAAAAAAAAAAAAA AAAAAAAAAAAAA
AAAAAAAAAAAAA AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAA tWRH AAAAAAAAAAAAAA
tRCS
tOEA
tRCH AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRRH
OE
V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC
I/O (Inputs)
V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VOH VOL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD tDZO tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEZ
Data Out
AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA tOFF AAAAAAAAAAAAAA
tCDD
I/O (Outputs)
tWRP
Write Cycle:
WE
V IH AAAAAAAAAAAA AAAAAAAAAAAA V IL AAAAAAAAAAAA AAAAAAAAAAAA
tWCS
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tRWL tCWL tWCH
tWRH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OE
V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDS
I/O (Inputs) I/O (Outputs)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V IH V IL HI-Z V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDH
Data In
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 24
HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM
Package Outlines
Plastic Package P-SOJ-42 (400 mil) (Small Outline J-lead, SMD)
0.8 min. 2.08 min. 3.75 max.
10.3 -0.3
B
1.27 0.43
+ 0.1 -
0.81 max. 0.18 A 42x 25.4 42 22 0.08
9.4
+ 0.25 -
11.2
+ 0.15 -
0.2 +0.12 -0.05
0.18 B
1)
GPJ05853
1
1)
21 27.43
-0.25
A
Index marking 1) does not include plastic or metal protusion of 0.15 max per side
Plastic Package P-TSOPII-50/44 (400 mil) (Thin Small Outline, SMD, 0.8 mm lead pitch)
Semiconductor Group
25

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